Altiumcustomize

Design Rule Verification Report

Date : 20.02.2010
Time : 20:43:01
Elapsed Time : 00:00:01
Filename : E:\My_Project\ALTIUM\J-LINK_v7\J-LINK_v7.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Hole Size Constraint (Min=0.254mm) (Max=5mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.09mm) (All),(All) 0
Silkscreen Over Component Pads (Clearance=0mm) (All),(All) 0
Silk to Silk (Clearance=0mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.2mm) (All) 0
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Room J-LINK_v7 (Bounding Region = (76.581mm, 73.025mm, 120.269mm, 175.514mm) (InComponentClass('J-LINK_v7')) 0
Total 0